Many very large scale integrated (VLSI) circuits are configured in a modular manner, in which previously designed and tested functional circuit blocks (sometimes referred to as Intellectual Property (IP) blocks) or devices are linked together to form larger circuits. The devices may be processing cores, memory controllers or peripherals, for example. To facilitate this, common interfaces have been defined.
More complex integrated circuits, such as System-on-Chip (SoC) circuits and circuits having multiple processing cores, for example, may transport data using a dedicated interconnect structure such as a bus or network. Devices may be connected via the interconnect structure may have one or more defined interfaces that include a data-bus of a specified width. An integrated circuit with multiple functional blocks may be configured as an interconnect network to enable efficient communication between functional blocks.
Processing cores are configured to use caches. When requested data is not present in the cache (referred to as a cache-miss) a direct memory transfer (DMT) may be used to retrieve the data via a memory controller. However, an interconnect structure may be used to couple devices with mismatched data-bus widths systems, where the processing cores, interconnect structure and memory controllers have varying data-bus widths. In systems with mismatched bus-widths, DMT is disabled because of differences in data widths. This results in increased latency when responding to a read request.